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ON Semiconductort
The MC74VHC245 is an advanced high speed CMOS octal bus transceiver fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. It is intended for two-way asynchronous communication between data buses. The direction of data transmission is determined by the level of the DIR input. The output enable pin (OE) can be used to disable the device, so that the buses are effectively isolated. All inputs are equipped with protection circuits against static discharge. * High Speed: tPD = 4.0ns (Typ) at VCC = 5V * Low Power Dissipation: ICC = 4A (Max) at TA = 25C * High Noise Immunity: VNIH = VNIL = 28% VCC * Power Down Protection Provided on Inputs * Balanced Propagation Delays * Designed for 2V to 5.5V Operating Range * Low Noise: VOLP = 1.2V (Max) * Pin and Function Compatible with Other Standard Logic Families * Latchup Performance Exceeds 300mA * ESD Performance: HBM > 2000V; Machine Model > 200V * Chip Complexity: 308 FETs or 77 Equivalent Gates
Octal Bus Transceiver
MC74VHC245
DW SUFFIX 20-LEAD SOIC WIDE PACKAGE CASE 751D-05
DT SUFFIX 20-LEAD TSSOP PACKAGE CASE 948E-02
M SUFFIX 20-LEAD SOIC EIAJ PACKAGE CASE 967-01 ORDERING INFORMATION MC74VHCXXXDW SOIC WIDE MC74VHCXXXDT TSSOP MC74VHCXXXM SOIC EIAJ
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These devices are available in Pb-free package(s). Specifications herein apply to both standard and Pb-free devices. Please see our website at www.onsemi.com for specific Pb-free orderable part numbers, or contact your local ON Semiconductor sales office or representative.
APPLICATION NOTES
* Do not force a signal on an I/O pin when it is an active output, * *
damage may occur. All floating (high impedance) input or I/O pins must be fixed by means of pull up or pull down resistors or bus terminator ICs. A parasitic diode is formed between the bus and VCC terminals. Therefore, the VHC245 cannot be used to interface 5V to 3V systems directly.
(c) Semiconductor Components Industries, LLC, 2006
March, 2006 - Rev. 5
1
Publication Order Number: MC74VHC245/D
A1 A2 A DATA PORT A3 A4 A5 A6 A7 A8 DIR OE
2 3 4 5 6 7 8 9 1 19
18 17 16 15 14 13 12 11
B1 B2 B3 B4 B5 B6 B7 B8 B DATA PORT
DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC OE B1 B2 B3 B4 B5 B6 B7 B8
Figure 1. LOGIC DIAGRAM
Figure 2. PIN ASSIGNMENT
FUNCTION TABLE
Control Inputs OE L L H DIR L H X Operation Data Transmitted from Bus B to Bus A Data Transmitted from Bus A to Bus B Buses Isolated (High-Impedance State)
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* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
III I I I I I I I I I I IIIIIIIIIIIII III I I I I I IIIIIIIIIIIII III I I III I I I I I IIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I IIIIIIIIIIII I II I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I IIIIIIIIIIIII III I I I I I IIIIIIIIIIIII III I I I I I I I I I I I I IIIIIIIIIIIII III I I I I I IIIIIIIIIIIII III I I I I I I I I I IIIIIIIIIIIIIIII IIII IIIIIII I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
SymbolIIIIIIIIIIIIII Parameter VCC Vout Tstg ICC IOK Iout Vin PD IIK Storage Temperature Power Dissipation in Still Air DC Supply Current, VCC and GND Pins DC Output Current, per Pin Output Diode Current Input Diode Current DC Output Voltage DC Input Voltage DC Supply Voltage SOIC Packages TSSOP Package - 0.5 to VCC + 0.5 - 65 to + 150 - 0.5 to + 7.0III V - 0.5 to + 7.0III V Value - 20 75 25 20 500 450 Unit mW mA mA mA mA _C V
DC ELECTRICAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
Symbol
Symbol
VOH
VOL
VCC
Vout
VIH
tr, tf
VIL
Vin
TA
Iin
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Input Rise and Fall Time
Operating Temperature
DC Output Voltage
DC Input Voltage
DC Supply Voltage
Parameter
Parameter
Vin = 5.5 V or GND (DIR, OE)
Vin = VIH or VIL IOL = 4mA IOL = 8mA
Vin = VIH or VIL IOL = 50A
Vin = VIH or VIL IOH = - 4mA IOH = - 8mA
Vin = VIH or VIL IOH = - 50A
Test Conditions
VCC = 3.3V 0.3V VCC =5.0V 0.5V
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0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 to 5.5 VCC V 3.0 4.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 - 40 Min 2.0 0 0 0 0 1.9 2.9 4.4
3 1.50 VCC x 0.7 2.58 3.94 Min + 85 Max VCC 100 20 5.5 5.5 TA = 25C Typ 0.0 0.0 0.0 2.0 3.0 4.5 ns/V Unit _C V V V 0.50 VCC x 0.3 0.1 0.36 0.36 Max 0.1 0.1 0.1 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. 1.50 VCC x 0.7 TA = - 40 to 85C 2.48 3.80 Min 1.9 2.9 4.4 0.50 VCC x 0.3 1.0 0.44 0.44 Max 0.1 0.1 0.1 Unit A V V V V
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DC ELECTRICAL CHARACTERISTICS
Symbol IOZ Parameter Test Conditions VCC V 5.5 TA = 25C Typ TA = - 40 to 85C Min Max 2.5 Min Max Unit A Maximum Three-State Leakage Current Maximum Quiescent Supply Current Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND 0.25 ICC 5.5 4.0 40.0 A
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol tPLH, tPHL Parameter
TA = 25C Typ 5.8 8.3 4.0 5.5
TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 10.0 13.5 6.5 8.5
Test Conditions
Min
Max 8.4 11.9 5.5 7.5
Unit ns
Maximum Propagation Delay, A to B or B to A
VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V RL = 1 k VCC = 5.0 0.5V RL = 1 k VCC = 3.3 0.3V RL = 1 k VCC = 5.0 0.5V RL = 1 k VCC = 3.3 0.3V (Note 1) VCC = 5.0 0.5V (Note 1)
CL = 15pF CL = 50pF CL = 15pF CL = 50pF
tPZL, tPZH
Output Enable Time OE to A or B
CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF
8.5 11.0 5.8 7.3
13.2 16.7
15.5 19.0 10.0 12.0 18.0 11.0 1.5 1.0 10
ns
8.5 10.6
tPLZ, tPHZ
Output Disable Time OE to A or B
11.5 7.0
15.8 9.7 1.5 1.0 10
ns
tOSLH, tOSHL
Output to Output Skew
ns ns
Cin
Maximum Input Capacitance DIR, OE Maximum Three-State I/O Capacitance
4 8
pF pF
CI/O
Typical @ 25C, VCC = 5.0V
21 CPD Power Dissipation Capacitance (Note 2) pF 1. Parameter guaranteed by design. tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25C Symbol VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Parameter Typ 0.9 -0.9 Max 1.2 -1.2 3.5 1.5 Unit V V V V
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SWITCHING WAVEFORMS
VCC GND VCC GND HIGH IMPEDANCE VOL +0.3V VOH -0.3V HIGH IMPEDANCE
DIR
50%
OE A or B tPLH 50% VCC A or B 50% tPHL VCC GND A or B
50% VCC tPZL 50% VCC tPZH 50% VCC tPHZ tPLZ
50% VCC
B or A
Figure 3.
Figure 4.
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5.
Figure 6.
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A1
2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 B8 B7 B6 B5 B4 B3 B2 B1
A2
A3
A4
A5
A6
A7
A8
DIR
1
OE
19
Figure 7. EXPANDED LOGIC DIAGRAM
DIR, OE
A, B
INPUT
I/O
Figure 8. INPUT EQUIVALENT CIRCUIT
Figure 9. BUS TERMINAL EQUIVALENT CIRCUIT
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OUTLINE DIMENSIONS DW SUFFIX SOIC CASE 751D-05 ISSUE F
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1 10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
DT SUFFIX TSSOP CASE 948E-02 ISSUE A
20X
K REF
M
L
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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IIII IIII IIII
SECTION N-N M DETAIL E
L/2
20
11
K K1
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
M SUFFIX SOIC EIAJ CASE 967-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e A VIEW P
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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